Microprocessor Interfacing

Output Coding

The examples used so far have been based on binary codes, where each bit in the

result represents a voltage value and the sum of these voltages in the output word

is the analog input voltage value. Some ADCs produce 2’s complement outputs,

where a negative voltage is represented by a negative 2’s complement value. A

few ADCs output values in BCD. Obviously this requires more bits for a given

range; a 12-bit binary output can represent values from 0 to 4095, but a 12-bit

BCD output can only represent values from 0 to 999.

Parallel Interfaces

ADCs come in a variety of interfaces, intended to operate with multiple processors.

Some parts include more than one type of interface to make them compatible

with as many processor families as possible.

The Maxim MAX151 is a typical 10-bit ADC with an 8-bit ‘‘universal’’ parallel

interface. As shown in Figure 2.11, the processor interface on the MAX151 has 8

data bits, a chip select (–CS), a read strobe (–RD), and a –BUSY output. The

MAX151 includes an internal S/H. On the falling edge of –RD and –CS, the S/H is

placed into hold mode and a conversion is started. If –CS and –RD do not go low

at the same time, the last falling edge starts a conversion. In most systems, –CS is

connected to an address decode and will go low before –RD. As soon as the

conversion starts, the ADC drives –BUSY low (active). –BUSY remains low until

the conversion is complete.

In the first mode of operation, which Maxim calls Slow Memory Mode, the

processor waits, holding –RD and –CS low, until the conversion is complete. In

such a system, the –BUSY signal would typically be connected to the processor –RDY

or –WAIT signal. This holds the processor in a wait state until the conversion

is complete. The maximum conversion time for the MAX151 is

The second mode of operation is called ROM mode. In this mode the

processor performs a read cycle, which places the S/H in hold mode and starts

a conversion. During this read, the processor reads the results of the previous

conversion. The –BUSY signal is not used to extend the read cycle. Instead, –BUSY

is connected to an interrupt, or is polled by the processor to indicate

when the conversion is complete. When –BUSY goes high, the processor does 

another read to get the result and start another conversion. Although the data

sheets refer to two different modes of operation, the ADC works the same way

in both cases:

.

Falling edge of –RD and –CS starts a conversion

.

.

As long as –RD and –CS stay low, current result remains available on bus

.

processor; if –RD and –CS are still low, this data replaces result of previous

conversion on bus

The MAX151 is designed to interface to most microprocessors. Actually interfacing

to a specific processor requires analysis of the MAX151 timing and how it

relates to the microprocessor timing.

When conversion completes, new conversion data is latched and available to the

Data Access Time

The MAX151 specifies a maximum access time of 180 ns over the full temperature

range (see Figure 2.12). This means that the result of a conversion will be

available on the bus nomore than 180 ns after the falling edge of –RD(assuming –CS

is already low when –RD goes low). The processor will need the data to be

stable some time before the rising edge of –RD. If there is a data bus buffer

between the MAX151 and the processor, the propagation delay through the

buffer must be included. This means that the processor bus cycle (the time that –RD

is low) must be at least as long as the access time of the MAX151, plus the

processor data setup time, plus any bus buffer delays.

–BUSY Output

The –BUSY output of the MAX151 goes low a maximum of 200 ns after the

falling edge of –RD. This is too long for the signal to directly drive most microprocessors

if you want to use the slow memory mode. Most microprocessors

require that the RDY or –WAIT signal be driven low earlier than this in the bus

cycle. Some require the wait request signal to be low one clock after –RD goes low.

The only solution to this problem is to artificially insert wait states to the bus cycle

until the –BUSY signal goes low. Some microprocessors, such as the 80188

family, have internal wait-state generators that can add wait states to a bus cycle.

The 80188 wait-state generator can be programmed to add 0, 1, 2, or 3 wait

states.

As shown in Figure 2.12, in Slow Memory mode the –BUSY signal goes high

just before the new conversion result is available; according to the datasheet, this

time is a maximum of 50 ns. For some processors, this means that the wait request

must be held active for an additional clock cycle after –BUSY goes high to ensure

that the correct data is read at the end of the bus cycle.

Current result is available on bus after read access time has elapsed 2:5 ms.